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Constant on-time control

There are three different more or less widely used types of constant on-time control. The first one is where the off-time is varied with an error signal. A loop with this type of control has a control-to-output voltage frequency response (or Bode plot if you prefer) similar to that of the constant-frequency voltage-mode control. The second one is where the off-time is terminated with a comparator that monitors the inductor current, and when that current goes below a level set by the error signal, the switch is turned on. This control (also called constant on-time valley-current control) has a control-to-output voltage frequency response similar to the constant-frequency valley-current control. The main difference is that its inner current-control loop does not suffer from the subharmonic instability of the constant-frequency version, so it does not require a stabilizing ramp and the control-to-output voltage response does not show the half-frequency peaking. The third version is where the off-time is terminated when the output voltage (or a fraction of it) goes below the reference voltage. This control belongs to the family of ripple-based controls and it cannot be characterized with the usual averaging-based control-to-output frequency response, for the reason that the gain is affected by the output ripple voltage itself.

As for the hysteretic control, the current-mode version is a close relative of the constant on-time valley-current-control. The version that uses the output ripple voltage instead of the inductor current ripple for turning on and off the switch (also called “hysteretic regulator”) is a close relative of the constant on-time ripple-based control.

Although the ripple-based control loops cannot be characterized with the usual Bode plots, the converters can still be unstable, but not in the meaning of the traditional control-loop instability that power-supply engineers are used to. Furthermore the hysteretic regulator is essentially unconditionally stable. The instabilities with ripple-based control are called “fast-scale” because the frequency of the instability is closely related to the switching frequency (either subharmonic, similar to the inner-loop instability of some of the current-mode controller, or chaotic in nature).

The paper I wrote a couple of years ago (“Ripple-Based Control of Switching Regulators—An Overview”) is a good introduction to ripple-based control and discusses some of the stability issues. There are also quite a few papers with detailed analyses on the stability of converters with feedback loops where the ripple content of the feedback signal is significant.

Impedance analyzer

A graphical impedance analyzer with good phase resolution is a must. Some brands have all the bells and whistles, but not the phase resolution necessary to accurately measure high Q (100+) components over the instrument’s full frequency range (which should extend at least into the low megahertz). Of course the Agilent 4294A fills the performance bill, but with a $40k+ purchase bill, it also empties the budget (like similar high end new models from Wayne Kerr). Used models from Wayne Kerr work very well, and can be had for under $10K but they are very heavy and clunky with very ugly (but still useable) displays.

Perhaps the best value may be the Hioki IM3570, which works extremely well with superior phase resolution, has a very nice color touch screen display (with all the expected engineering graphing formats), is compact and lightweight, and costs around $10k new. Its only downside is that its fan is annoyingly loud and does not reduce its noise output during instrument idle.

But where should an impedance analyzer rank on the power electronics design engineer’s basic equipment list (and why)?

Beyond the basic lower cost necessities such as DMMs, bench power supplies, test leads, soldering stations, etcetera, I would rank a good impedance analyzer second only to a good oscilloscope. The impedance analyzer allows one to see all of a component’s secondary impedance characteristics and to directly compare similar components. Often overlooked is the information such an instrument can provide by examining component assemblies in situ in a circuit board assembly. Sometimes this can be very revealing of hidden, but influential layout parasitics.

Equally importantly, an impedance analyzer allows accurate SPICE models to be quickly formulated so that simulation can be used as a meaningful design tool. Transformer magnetizing and leakage inductances can be measured as well as inter-winding capacitance and frequency dependent resistive losses. From these measurements and with proper technique, a model can be formulated that nearly exactly matches the real part. Not only does this allow power circuits and control loops to be initially designed entirely by simulation (under the judicious eye of experience, of course), but it even allows one to effectively simulate the low frequency end of a design’s EMI performance.

FETs in ZVS bridge

Had run into a very serious field failure issue a decade ago due to IXYS FETs used in a phase-shifted ZVS bridge topology. Eventually, the problem was tracked to failure of the FETs’ body diode when the unit operated at higher ambient temperature.

When FETs were first introduced for use in hard switching applications, it was quickly discovered that under high di/dt commutating conditions, the parasitic bipolar transistor that forms the body diode can turn on resulting in catastrophic failure (shorting) of the FET. I had run into this issue in the mid ’80s and if memory serves me correctly, IR was a leader in making their FET body diodes much more robust and capable of hard commutation. Having had this experience with FET commutation failures and after exhausting other lines of investigation which showed no problem with the operation of the ZVS bridge, I built a tester which could establish an adjustable current through the body diode of the FET under test followed by hard commutation of the body diode.

Room temperature testing of the suspect FET showed the body diode recovery characteristic similar to that of what turned out to be a more robust IR FET. Some difference was seen in the diode recovery as the IXYS FET was a bit slower and did show higher recovered charge. However, was unable to induce a failure in either the IXYS or IR FET even when commutating high values of forward diode current up to 20A when testing at room temperature.

The testing was then repeated in a heated condition. This proved to be very informative. The IXYS FETs were found to fail repeatedly with a case temperature around 80C and forward diode current prior to commutation as low as 5A. In contrast, the IR devices were operated to 125C case temp with forward diode currents of 10A without failure.

This confirmed a high temperature operating problem of the IXYS FETs associated with the body diode. Changing to the more robust IR devices solved the field failure issue.
Beware when a FET datasheet does not provide body diode di/dt limits at elevated ambient.

A more complete explanation of the FET body diode failure mechanism in ZVS applications can be found in application note APT9804 published by Advanced Power Technology.

I believe FETs can be reliably used in ZVS applications if the devices are carefully selected and shown to have robust body diode commutation characteristics.

Paralleling IGBT modules

I’m not sure why the IGBTs would share the current since they’re paralleled, unless external circuitry (series inductance, resistance, gate resistors) forces them to do so?

I would be pretty leery of paralleling these modules. As far as the PN diodes go, reverse recovery currents in PN diodes (especially if they are hard switched to a reverse voltage) are usually not limited by their internal semiconductor operation until they reach “soft recovery” (the point where the reverse current decays). They are usually limited by external circuitry (resistance, inductance, IGBT gate resistance). A perfect example: the traditional diode reverse recovery measurement test externally limits the reversing current to a linear falling ramp by using a series inductance. If you could reverse the voltage across the diode in a nanosecond, you would see an enormous reverse current spike.

Even though diode dopings are pretty well controlled these days, carrier lifetimes are not necessarily. Since one diode might “turn off” (go into a soft reverse current decreasing ramp, where the diode actually DOES limit its own current) before the other, you may end up with all the current going through one diode for a least a little while (the motor will look like an inductor, for all intents and purposes, during the diode turn-off). Probably better to control the max diode current externally for each driver.

Paralleling IGBT modules where the IGBT but not the diode has a PTC is commonly done at higher powers. I personally have never done more than 3 x 600A modules in parallel but if you look at things like high power wind then things get very “interesting”. It is all a matter of analysis, good thermal coupling, symmetrical layout and current de-rating. Once you get too many modules in parallel then the de-rating gets out of hand without some kind of passive or active element to ensure current sharing. Then you know it is time to switch to a higher current module or a higher voltage lower current for the same power. The relative proportion of switching losses vs conduction losses also has a big part to play.

Power converter trend

The trend toward lower losses in power converters is not apparent in all of the applications of power converters. It is also not apparent that the power converter solution and its losses for a given market will be the same when it comes to losses. In terms of the market shift that you mention, Prof. the answer is probably that each market is becoming split into a lower efficiency and higher efficiency solution.

From my limited view the reason for this is the effort and time required to do the low loss development. The early developers of low loss converters are now ahead and those that were slower may never catch them. This gap is in a number of converter markets widening, with both higher loss and lower loss offerings continuing to be used and sold. This split is not apparent with different levels of development or geographically.

Some markets already have very efficient solutions, other markets not so efficient and others had high power loss solutions. The customers accepted these solutions. The path to lower loss converters is for some markets not yet clear and in some markets the requirement may never actually become real.

It does seem that there is a real case to make for any power converter market splitting in two as the opportunities presented by lowering the power loss are taken.

All low loss converters present significant challenges and are all somewhat esoteric.

For me power supply EMI control consists of designing filtering for differential and common mode conducted emissions. The differential mode filtering attenuates the primary side differential lower frequency switching current fundamental & harmonic frequencies. The common mode filtering provides a low impedance return path for high frequency noise currents resulting from high dV/dt transitions during switching transitions present on the power semiconductors (switching mosfet drain, rectifier cathods). These noise currents ring at high frequencies as they oscillate in the uncontrolled parasitic inductance and capacitance associated with their return to source path. Shortening and damping this return path allows the high frequency noise currents to return locally instead of via the measurement copper bench and conducted emi current or voltage (LISN) probe as well as providing a more damped ringing frequency. Shorting this return path has the added benefit of decreasing radiated emissions. In addition proper layout of the power train so as to minimize the loop area associated with both the primary and secondary side switching currents minimizes the associated radiated emissions.

When I mentioned the criticism of resonant mode converter as related to the challenges of emi filitering I was referring to the additional differential mode filtering required. For example if you take a square wave primary side current waveform and analyze the differential frequency content the fundamental magnitude with be lower and there will be higher frequency components as compared to a purely resonant approach at the same power level. It is normally the lower frequency content that has to be filtered differentially.

Given these differences the additional emi filtering volume/cost of the resonant approach may pose a disadvantage.

Conditional stability

Conditional stability, I like to think about it this way:

The ultimate test of stability is knowing whether the poles of the closed loop system are in the LHP. If so, it is stable.

We get at the poles of the system by looking at the characteristic equation, 1+T(s). Unfortunately, we don’t have the math available (except in classroom exercises) we have an empirical system that may or may not be reduced to a mathematical model. For power supplies, even if they can be reduced to a model, it is approximate and just about always has significant deviations from the hardware. That is why measurements persist in this industry.

Nyquist came up with a criterion for making sure that the poles are in the LHP by drawing his diagram. When you plot the vector diagram of T(s) is must not encircle the -1 point.

Bode realized that the Nyquist diagram was not good for high gain since it plotted a linear scale of the magnitude, so he came up with his Bode plot which is what everyone uses. The Bode criteria only says that the phase must be above -180 degrees when it crosses over 0 dB. There is nothing that says it can’t do that before 0 dB.

If you draw the Nyquist diagram of a conditionally stable system, you’ll see it doesn’t surround the -1 point.

If you like, I can put some figures together. Or maybe a video would be a good topic.

All this is great of course, but it’s still puzzling to think of how a sine wave can chase itself around the loop, get amplified and inverted, phase shifted another 180 degrees, and not be unstable!

Having said all this about Nyquist, it is not something I plot in the lab. I just use it as an educational tool. In the lab, in courses, or consulting for clients, the Bode plot of gain and phase is what we use.

How to suppress chaotic operation in a DCM flyback at low load

I would like to share these tips with everybody.
A current mode controlled flyback converter always becomes unstable at low load due to the unavoidable leading edge current spike. It is not normally dangerous but as a design engineer I don’t like to look at it and listen to it.

Here are three useful and not patented tips.

First tip:
• Insert a low pass filter, say 1kohm + 100pF between current sense resistor and CS input in your control IC.
• Split the 1kohm in two resistors R1 to the fet and R2 to the control IC. R1 << R2.
• Insert 0,5 – 1pF between drain and the junction R1/R2. This can be made as a layer-to-layer capacitor in the PCB. It does not have to be a specific value.
• Adjust R1 until the spike in the junction in R1/R2 is cancelled.
You will see that the current spike is always proportional to the negative drain voltage step at turn-on. Once adjusted, the cancellation always follows the voltage step, and you some times achieve miracles with it. Cost = one resistor.

Second tip:
Having the low pass filter from first tip, add a small fraction of the gate driver output voltage to the current sense input, say 0,1V by inserting a large resistor from ‘Drive Out’ to ‘CS input’. The added low pass filtered step voltage will more or less conceal the current spike. You should reduce your current sense resistor accordingly. Cost = one resistor.

Third tip:
In a low power flyback, you some times just need an RC network or just an extra capacitor from drain to a DC point, either to reduce overshoot or to reduce noise. Connect the RC network or the capacitor to source, not to ground or Vcc. If you connect it to ground or Vcc, you will measure the added discharge current peak in the current sense resistor. Cost = nothing – just knowledge.

All tips can be used individually or combined => Less need for pre-load resistors on your output.

Right Half Plane Pole

Very few know about the Right Half Plane Pole (not a RHP-Zero) at high duty cycle in a DCM buck with current mode control. Maybe because it is not really a problem.
It is said that this instability starts above 2/3 duty cycle – I think that must be with a resistive load. If loaded with a pure current source, it starts above 50% duty cycle.

Here is a little down-to-earth explanation:
If you run a buck converter at high duty cycle but DCM, it probably works fine and is completely stable. Then imagine you suddenly open the feedback loop, leaving the peak current constant and unchanged. The duty cycle will then rush either back to 50% or to 100% if possible. You now have a system with a negative output resistance – if Voltage goes up, the output current will increase.

You can see it by drawing some triangles on a piece of paper: A steady state DCM current triangle with an up-slope longer than the down-slope and a fixed peak value. Now, if you imagine that the output voltage rises, you can draw a new triangle with the same peak current. The up-slope will be longer, the down-slope will be shorter but the sum of times will be longer than in the steady state case. The new triangle therefore has a larger area than the steady state triangle, which means a higher average output current. So higher output voltage generates higher output current if peak current is constant. Loaded with a current source, it is clear that this is an unstable system, like a flipflop, and it starts becoming unstable above 50% duty cycle.

However, when you close the feedback loop, the system is (conditionally) stable and the loop gain is normally so high at the RHP Pole frequency that it requires a huge gain reduction to make it unstable.

It’s like when you drive on your bike. A bike has two wheels and therefore can tilt to either side – it is a system with a low frequency RHPP like a flipflop. If you stand still, it will certainly tilt to the left or to the right because you have no way to adjust your balance back. But if you drive, you have a system with feedback where you can immediately correct imbalance by turning the handlebars. As we know, this system is stable unless you have drunk a lot of beers.

Experience: Flyback

My first SMPS design was a multiple output flyback. This was in 1976, when there were no PWM controllers. So I used a 556 (1/2 osc -30 kHz, and 1/2 PWM generator) plus used a 3904 NPN where the VBE was the reference and also provided gain for the error amp function. I hap-hazardly wound the windings on a 25 mm torroid. It ranglike a tank circuit. I quickly abandoned the transformer and after a year, and many hours on the bench, I had a production-grad SMPS.
Since it went into a private aircraft weather reader system, I needed an exterier SMPS which was a buck converter. I used an LM105 linear regulator with positive feedback to make it oscillate (one of nationals ap notes). It worked, but I soon learned that the electrolytic capacitors lost all of their capacitance at -25 deg C. It later worked with military-grade capacitors.

I had small hills of dead MOSFETs and the directly attached controllers. When the first power MOSFETs emerged in 1979, I blew-up so many that I almost wrote them off. They had some real issues with D-S voltage overstress. They have come a long way since.

As far as very wide range flyback converter, please dig-up AN1327 on the ONSEMI website. This describes a control strategy (fixed off-time, variable on-time) and the transformer design.
The processor to that was a 3W flyback that drove 3 floating gate drive circuits and had an input range of 85 VAC to 576 VAC. It was for a 3 phase industrial motor drive. The toughest area was the transformer. To meet the isolation requirements of the UL, and IEC, it would have required a very large core, and bobbin plus a lot of tape. The PCB had the dimensions of 50 mm x 50 mm and 9 mm thick A magnetics designer named Jeff Brown from Cramerco.com is now my magnetics God. He designed me a custom core and bobbin that was 10 mm high on basically an EF15 sized core. The 3 piece bobbin met all of the spacing requirements without tape. The customer was expecting a 2 – 3 tier product offering for the different voltage ranges, but instead could offer only one. They were thrilled.

Can be done, watch your breakdown voltages, spacings and RMS currents. I found that around 17 -20 watts is about the practical limit for an EF40 core before the transformer RMS currents get too high.

Experience: Design

I tell customers that at least 50% of the design effort is the layout and routing by someone who knows what they are doing. Layer stackup is very critical for multiple layer designs. Yes, a solid design is required. But the perfect design goes down in flames with a bad layout. Rudy Severns said it best in one of his early books that you have to “think RF” when doing a layout. I have followed this philosophy for years with great success. Problems with a layout person who wants to run the auto route or doesn’t understand analog layout? No problem, you, as the design engineer, do not have to release the design until it is to your satisfaction.

I have had Schottky diodes fail because the PIV was exceeded due to circuit inductance causing just enough of a very high frequency ring (very hard to see on a scope) to exceed the PIV. Know your circuit Z’s, keep your traces short and fat.

Fixed a number of problems associated with capacitor RMS ratings on AC to DC front ends. Along with this is the peak inrush current for a bridge rectifier at turn on and, in some cases, during steady state. Unit can be turned on at the 90 deg phase angle into a capacitive load. This must be analyzed with assumptions for input resistance and/or a current inrush circuit must be added.

A satellite power supply had 70 deg phase margin on the bench, resistive load, but oscillated on the real load. Measured the loop using the AP200 on the load and the phase margin was zero. Test the power supply on the real load before going to production and then a random sampling during the life of the product.

I used MathCAD for designs until the average models came out for SMPS. Yes, the equations are nice to see and work with but they are just models none the less. I would rather have PsPice to the math while I pay attention to the models used and the overall design effort. Creating large closed form equations is wrought with pitfalls, trapdoors, and landmines. Plus, hundreds of pages of MathCAD, which I have done, is hard to sell to the customer during a design review (most attendees drift off after page 1). The PsPice schematics are more easily sold and then modified as needed with better understanding all around.